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rt8800a 1 ds8800a-06 april 2011 www.richtek.com features z z z z z 5v power supply voltage z z z z z 2/3-phase power conversion with automatic phase selection z z z z z output voltage controlled by external reference voltage z z z z z precise core voltage regulation z z z z z power stage thermal balance by dcr current sensing z z z z z extreme low-cost, lossless time sharing current sensing z z z z z internal soft-start z z z z z hiccup mode over-current protection z z z z z over voltage protection z z z z z adjustable operating frequency and typical at 300khz per phase z z z z z power good indication z z z z z small 16-lead vqfn package z z z z z rohs compliant and 100% lead (pb)-free applications z desktop cpu core power z low output voltage, high power density dc/dc converters z voltage regulator modules general purpose 3-phase pwm controller for high-density power supply ordering information marking information for marking information, contact our sales representative directly or through a richtek distributor located in your area. note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. general description the rt8800a is a general-purposed multi-phase synchronous buck controller dedicating for high power density applications. the rt8800a operates with 2 or 3 synchronous buck switching stages in interleaved phase set automatically. the multiphase architecture provides high output current while maintaining low power dissipation on power devices and low stress on input and output capacitors. the output voltage is precisely regulated to the external reference voltage at pi pin. the rt8800a can provide intel ? vrd10.x or amd ? k8 compliant output voltage when companioned with dac generator rt9401a/b. the rt8800a adopts innovative time-sharing dcr current sensing technique for channel current balance, droop tuning, and over current protection. using one common gm amplifier for current sensing eliminates offset errors and linearity variation between gms. as sub-milli-ohm- grade inductors are widely used in modern mother boards, slight mismatch of gm amplifiers offset and linearity results in considerable current shift between phases. the time- sharing dcr current sensing technique is extremely important to guarantee phase current balance at mass production. other features include overvoltage protection, undervoltage protection and internal softstart. the rt8800a comes to a vqfn-16l 3x3 package. package type qv : vqfn-16l 3x3 (v-type) lead plating system p : pb free g : green (halogen free and pb free) rt8800a
rt8800a 2 ds8800a-06 april 2011 www.richtek.com functional pin description imax (pin 1) over current protection setting. vid125 (pin 2) connect a resistor from this pin to gnd can raise v out . fb (pin 3) the pin is defined as the inverting input of internal error amplifier. dvd (pin 4) the pin is defined as a programmable power uvlo detection input. trip threshold = 0.8v at v dvd rising. comp (pin 5) the pin is defined as the output of the error amplifier and the input of all pwm comparators. pi (pin 6) the pin is defined as the positive input of the error amplifier. rt (pin 7) switching frequency setting. connect this pin to gnd with a resistor to set the frequency. icommon (pin 8) common negative input of current sense amplifiers for all three channels. pgood (pin 9) output power-good indication. the signal is implemented as an output signal with open-drain type. isp1 , isp2 , isp3 (pin 12, pin 11, pin 10) current sense positive inputs for individual converter channel current sense. pwm1 , pwm2 , pwm3 (pin 13, pin 14, pin 15) pwm outputs for each phase switching drive. vdd (pin 16) chip power supply. connect this pin to a 5v supply. gnd [exposed pad (17)] the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. pin configurations (top view) vqfn-16l 3x3 imax isp1 pgood isp3 isp2 dvd fb vid125 icommon comp pi rt pwm1 vdd pwm3 pwm2 12 11 10 9 13 14 15 16 1 2 3 4 8 7 6 5 gnd 17
rt8800a 3 ds8800a-06 april 2011 www.richtek.com 3-phase with rt9401a/b dac generator typical application circuit phase3 phase2 phase1 pi vid125 imax pgood pwm3 pwm2 isp3 isp2 fb comp vdd pwm1 rt dvd icommon isp1 3.3v 12v v core 5v 9 3 5 4 7 2 8 12 11 10 14 15 13 16 1 6 gnd 15k 10nf 33pf 3k 4.7uf optional optional optional 1uf 1uf 1uf 430 3k 16k 27k 10k 10k r r r rt8800a boot2 pwm3 pwm2 pwm1 boot1 lgate3 pvcc3 phase3 ugate3 boot3 ugate2 pvcc2 phase2 lgate2 ts ugate1 pvcc1 phase1 lgate1 vdd 12v 5v sb phase1 v in phase2 v core phase3 1242223 9 10 11 15 14 3 8 20 21 19 17 16 7 5 4 2 gnd 12v 12v 12v v in 12v 1uf 1000uf 1uh 0 1uf 1uf 0 10 1uf 3.3nf 2.2 1uf 0 1uf 0 3.3uf 2.2 0.5uh 0.5uh 0.5uh 1uf 0 3.3nf 2.2 0 1uf 10uf x 4 1000uf x 12 rt9605 1500uf x 4 12v v in optional optional r adj r comm r csn 16k 10nf rt9401a/b vid1 vdd vid0 vid3 vda gnd vid2 vid4 5v 1 2 3 4 5 6 7 8 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 to c14 c15 c16 c17 c18 c19 c20 c21 c22 c23 c24 c25 to c36 c37 to c40 d1 d2 q1 q2 q3 q4 q5 q6 q7 q8 q9 l1 l2 l3 r cs d sky
rt8800a 4 ds8800a-06 april 2011 www.richtek.com function block diagram oscillator & ramp generator + + + + + + sample & hold pwm1 pwm2 pwm3 ocp sum/n & ocp detection pgood dvd gnd soft start + + - icommon isp1 isp2 isp3 pwm logic & driver pwmcp + - pwm logic & driver pwmcp + - pwm logic & driver pwmcp + - + + + mux mux sample & hold sample & hold vdd fb ea gm comp - + - 0.8v v ref pi inh inh inh power on reset rt maj 500mv ovp vid125 imax
rt8800a 5 ds8800a-06 april 2011 www.richtek.com absolute maximum ratings (note 1) z supply voltage, v dd ------------------------------------------------------------------------------------------- 7v z input, output or i/o voltage ---------------------------------------------------------------------------------- gnd ? 0.3v to v dd + 0.3v z power dissipation, p d @ t a = 25 c vqfn-16l 3x3 -------------------------------------------------------------------------------------------------- 1.47w z package thermal resistance (note 2) vqfn-16l 3x3, ja --------------------------------------------------------------------------------------------- 68 c/w z junction temperature ------------------------------------------------------------------------------------------ 150 c z lead temperature (soldering, 10 sec.) -------------------------------------------------------------------- 260 c z storage temperature range --------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body mode) ----------------------------------------------------------------------------------- 2kv mm (ma chine mode) ------------------------------------------------------------------------------------------- 200v electrical characteristics (v dd = 5v, t a = 25c, unless otherwise specified) parameter symbol test conditions min typ max unit v dd supply current nominal supply current i dd pwm 1,2,3 open -- 5 -- ma power-on reset rising 4.0 4.2 4.5 v dd threshold hysteresis 0.2 0.5 -- v dvd rising threshold 0.75 0.8 0.85 v dvd hysteresis -- 65 -- mv oscillator free running frequency f osc r rt = 16k 170 200 230 khz frequency adjustable range f osc_adj 50 -- 400 khz ramp amplitude v osc r rt = 16k -- 1.7 -- v ramp valley v rv -- 1.0 -- v maximum on-time of each channel 62 66 75 % rt pin voltage v rt r rt = 16k 0.77 0.82 0.87 v reference voltage imax reference voltage v imax r imax = 16k 0.75 0.8 0.85 v vid125 reference voltage v vid125 r vid125 = 16k 0.75 0.8 0.85 v recommended operating conditions (note 4) z supply voltage, v dd ------------------------------------------------------------------------------------------- 5v 10% z ambient temperature range --------------------------------------------------------------------------------- 0 c to 70 c z junction temperature range --------------------------------------------------------------------------------- 0 c to 125 c to be continued
rt8800a 6 ds8800a-06 april 2011 www.richtek.com parameter symbol test conditions min typ max unit error amplifier dc gain -- 65 -- db gain-bandwidth product gbw c l = 10pf -- 10 -- mhz slew rate sr c l = 10pf -- 8 -- v/ s current sense gm amplifier recommended full scale source current 100 -- -- a protection over-voltage trip (v fb ? v pi ) 360 460 560 mv power good pgood output low voltage v pgood i pgood = 4ma -- -- 0.2 v pgood delay t pgood_delay 90% * v out to pgood_h 4 -- 8 ms note 1. stresses listed as the above "absolute maximum ratings" may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in the natural convection at t a = 25 c on a low effective thermal conductivity test board of jedec 51-3 thermal measurement standard. note 3. devices are esd sensitive. handling precaution recommended. note 4. the device is not guaranteed to function outside its operating conditions.
rt8800a 7 ds8800a-06 april 2011 www.richtek.com v vid125 vs. temperature 0.78 0.785 0.79 0.795 0.8 0.805 0.81 0.815 -25 -10 5 20 35 50 65 80 95 110 125 temperature v vid125 (v) gm 0 10 20 30 40 50 60 70 80 90 0 102030405060708090100110 v c (mv) i adj (ua) typical operating characteristics ( c) gm3 gm2 gm1 frequency vs. r rt 0 100 200 300 400 500 600 700 800 900 1000 0 5 10 15 20 25 30 35 40 45 50 55 60 r rt (k [ ) frequency (khz) (k ) load line 1.24 1.26 1.28 1.3 1.32 1.34 1.36 1.38 1.4 0 102030405060708090100 output current (a) output voltage (v) r ll = 1.5m , r csn = 10k , r adj = 100 v in = 12v efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 0 102030405060708090100 output current (a) efficiency (%) driver rt9605 v in = 12v, v out = 1.4v gm3 gm2 gm1 r comm = 430 frequency vs. temperature 0 50 100 150 200 250 300 350 -25-105 203550658095110125 temperature frequency (khz) ( c) r rt = 16k
rt8800a 8 ds8800a-06 april 2011 www.richtek.com time (25 s/div) vid on the fly falling v fb (200mv/div) vid0 (2v/div) pwm (5v/div) v core (100mv/div) i out = 5a time (2.5 s/div) load transient response ugate1 (20v/div) v core (200mv/div) ugate2 (20v/div) ugate3 (20v/div) phase 1, i out = 5a to 85a @sr = 93a/us) time (2.5 s/div) load transient response ugate1 (20v/div) v core (200mv/div) ugate2 (20v/div) ugate3 (20v/div) phase 3, i out = 5a to 85a @sr = 93a/us) time (10ms/div) over current protection i l1 +i l2 (50a/div) v core (1v/div) pwm1 (10v/div) v comp (2v/div) short while turn_on time (10ms/div) over current protection i l1 +i l2 (50a/div) v comp (2v/div) pwm1 (10v/div) v core (1v/div) short after turn_on time (2.5 s/div) load transient response ugate1 (20v/div) v core (200mv/div) ugate2 (20v/div) ugate3 (20v/div) phase2, i out = 5a to 85a @sr = 93a/us)
rt8800a 9 ds8800a-06 april 2011 www.richtek.com time (10 s/div) vid on the fly rising i out = 5a v fb (200mv/div) vid0 (2v/div) pwm (5v/div) v core (200mv/div) time (10 s/div) vid on the fly rising i out = 90a v fb (200mv/div) vid0 (2v/div) pwm (5v/div) v core (200mv/div) time (25 s/div) vid on the fly falling v fb (200mv/div) vid0 (2v/div) pwm (5v/div) v core (50mv/div) i out = 90a
rt8800a 10 ds8800a-06 april 2011 www.richtek.com applications information the rt8800a is a general-purposed multi-phase synchronous buck controller dedicating for high power density applications. the rt8800a operates with 2 or 3 synchronous buck switching stages in interleaved phase set automatically. the multiphase architecture provides high output current while maintaining low power dissipation on power devices and low stress on input and output capacitors. initialization the rt8800a initiates after 2 pins are ready : vdd pin power on reset (por) and dvd pin is higher than 1v. vdd por is to make sure rt8800a is powered by a voltage high enough for normal work. the rising threshold voltage of vdd por is 4.2v typically. at vdd por, rt8800a checks pwm3 status to determine phase number of operation. pull high pwm3 for two-phase operation. the unused current sense pins should be connected to gnd or left floating. dvd is to make sure that a tx12v is ready for the companion mosfet drivers to work normally. connect a voltage divider from atx12v to dvd pin as shown in the typical application circuit. make sure that dvd pin voltage is below its threshold voltage before drivers are ready and above its threshold voltage for minimum atx12v during normal operation. if one of vdd and dvd is not ready, rt8800a keeps its pwm outputs high impedance and the companion drivers turn off both upper and lower mosfets. soft-start after vdd and dvd are ready, rt8800a initiates its soft start cycle as shown in figure 1. the error amplifier and pwm comparator are triple-input devices. the non-inverting input whichever is smaller dominates the behavior of the device. the soft start function generates ss and sse for the non-inverting input of pwm comparator and error amplifier respectively where sse = ss - v gs . vgs is threshold voltage of internal mosfet. the typical soft- start duration is 3ms. the soft start can be sliced to several time frames with specific operation respectively. 1) mode 1 (ss < v ramp_valley ) initially the comp stays in the positive saturation due to offset of the error amplifier. since ss < v ramp_valley , the pwm comparator keeps its output low and v out is zero. 2) mode 2 (v ramp_valley < ss < cross-over) since v ramp_valley < ss < cross-over, ss dominates the non-inverting inputs of the pwm comparators. the pwm duty cycles increase according to the ramping up ss signal. the output voltage ramps up accordingly. however as v out increases, the difference between v out and sse (ss - v gs ) is reduced and comp leaves the saturation and declines. the takeover of ss lasts until it meets the comp. during this interval, since the feedback path is broken, the converter is operated in the open loop. 3) mode3 (cross-over < ss < v gs + v pi ) when the v comp takes over the non-inverting input for pwm amplifier and when sse (ss - v gs ) < v pi , the output of the converter follows the ramp input, sse (ss - v gs ). before the crossover, the output follows ss signal. and when v comp takes over ss, the output is expected to follow sse (ss - v gs ). therefore the deviation of v gs is represented as the falling of v out for a short while. the comp is observed to keep its decline when it passes the cross-over, which shortens the duty width and hence the falling of v out happens. since there is a feedback loop for the error amplifier, the output's response to the ramp input, sse (ss - v gs ) is lower than that in mode 2. 4) mode 4 (ss > v gs + v pi ) when ss > v gs + v pi , the output of the converter follows the desired v pi signal and the soft start completes. however, the ss keeps ramping up to 3.3v and stays there. the pgood pin trips to high impedance as ss reaches 3.3v. + + + - + - soft start fb pi ss sse ea pwm figure 1. soft start block diagram.
rt8800a 11 ds8800a-06 april 2011 www.richtek.com figure 2 comp v core sse_internal ss_internal cross-over v ramp_valley time-sharing dcr current sensing rt8800a adopts an innovative time-sharing dcr current sensing technique to sense the phase currents for phase current balance (phase thermal balance), over current protection and load line regulation as shown in figure 3. the current sensing amplifier gm samples and holds voltages v x across the current sensing capacitor c x by turns in a switching cycle. according to the basic circuit theory, if lx lx x x x lx x r i v then c r r l = = consequently, the sensing current i x is proportional to inductor current i lx and is expressed as the sensed current i x is used for current balance, over current protection, and droop tuning as described as followed. since all phases share one common gm, gm offset and linearity variation effect are eliminated in practical applications. as sub-milli-ohmgrade inductors are widely used in modern motherboards, slight mismatch of gm amplifiers offset and linearity results in considerable current shift between phases. the time sharing dcr current sensing technical is extremely important to guarantee phase current balance at mass production. comm lx lx x r r i i = figure 3 figure 4 and 5 show the linearity of gm amplifier and its test circuit respectively. a voltage source is applied to ispx while other ispx pins are short to v out . the voltage v adj across resistor r adj is measured. it is observed from figu re 5 shows that all ispx share the same transconductance linearity and voltage offset. figure 4. the linearity of gmx v out t1 t3 t2 i x s/h ckt + - l x r lx r comm i lx + r x c x + v x - gm 0 10 20 30 40 50 60 70 0 20406080100 v c (mv) i adj (ua) gm1 gm2 gm3 v x
rt8800a 12 ds8800a-06 april 2011 www.richtek.com figure 5. test circuit of gm. phase current balance the sampled and held phase current i x are injected to the corresponding saw tooth waveforms of pwm comparators. if phase current i x is larger than other phase currents, its saw tooth waveform will be lift higher than the others. the rt8800a reduces the duty cycle of corresponding phase to decrease the phase current accordingly, vice versa. over current protection rt8800a uses an external resistor r imax connected to imax pin to generate a reference current i imax for over current protection: imax imax imax r v i = where v imax is 0.8v ty pical. ocp comparator compares each sensed phase current i x with this reference current as shown in figure 6. equivalently, the maximum phase current is calculated as : lx comm imax imax lx(max) r r r v 2 3 i = figure 6. over current comparator. + - 1/3 i x 1/2 i imax ocp comparator the rt8800a uses hiccup mode to eliminate nuisance detection of ocp or reduce output current when output is shorted to ground as shown in figure 7 and 8. the rt8800a shuts down and latches off afte r 3 time ocp hiccups. it can only restart by resetting one of vdd or dvd pin. figure 7. the over current protection in the interval figure 8. over current protection at steady state (5v/div) over current protection time (25ms/div) pwm i l (5v/div) voltage reference for converter output & load droop the output voltage is sensed at fb pin. the rt8800a receives an external reference voltage at pi pin as the non-inverting of the error amplifier and precisely regulates the fb voltage to this reference voltage. the rt8800a can provide intel ? vrd10.x or amd ? k8 compliant output voltage when companioned with dac generator rt9401a/b as shown in figure 9. the rt9401a/b receives vid[0:4] and produces dac_out that complies with vrd10.x or k8 vid table. the dac_out is fed to pi pin through a resistor r adj as the reference voltage of the error amplifiers. the vid125 provides a 12.5mv offset for full compliance of vrd10.x table. over current protection time (25ms/div) pwm v ss (5v/div) (5v/div) + - mux mux s/h sum/n + - + - isp1 isp2 isp3 icommon ea pi rt9401 r adj + v adj - i adj gm i x v x v core dac_out
rt8800a 13 ds8800a-06 april 2011 www.richtek.com figure 9 comm lx adj core core r x 3 r x r i v line load ? = = dead zone elimination and output voltage offset function rt8800a samples and holds inductor valley current by time-sharing sourcing a current i x to r comm . at light load condition the inductor valley current and consequently the voltage v x across the sensing capacitor may be negative. figure 10 figure 11 referring to figure 11, the schottky diode provides a constant voltage drop v f with enough bias current. i x is expressed as: comm lx lx_valley csn lx lx_valley f x r r i r r i v i + + = to make sure rt8800a could sense the inductor current, right hand side of equation (1) should always be positive: 0 r r i r r i v comm lx lx_valley csn lx lx_valley f + + since v f >> (i lx_valley x r lx ) in practical application, equation (2) could be simplified as: comm lx lx_valley csn f r r i r v (1) (2) (3) droop and load lind setting the sampled and held phase current i x are summed to get sum(i x ). rt8800a then sinks a current that is 1/3 sum(i x ) and produces a droop voltage that is proportional to the average phase voltage. v adj = 1/3 sum(i x ) x r adj v adj is th en subtracted form dac generator output as the real reference voltage at non-inverting input of the error amplifier. consequently, load line slope is calculated as: v core i core dac_out v offset r csn < r csn = r csn > load line spec_high spec_low + - r comm r csn d sky r cs v core - v f c x + v x - r x l x r l_x i x i l v core output voltage offset function vid125 pin is internally regulated to be around 0.8v. an external resistor r vid125 between vid125 and gnd generates the offset current . fb pin will sink a current which is half of i ofs because of a current mirror fb and vid125. the output offset voltage is calculated to be ofs vid125 0.8v i = r ofs fb vid125 0.8v 1 v r r2 = fb core fb ofs fb vid125 0.8v r v v + v v 2r + == thus, the output voltage becomes note : to maintain vid125 voltage around 0.8v, r vid125 must not be less than 16k . a negative i x is required to correctly sense the negative voltage. however, the rt8800a cannot provide a negative i x and consequently cannot sense negative inductor current. this results in dead zone of load line performance as shown in figure 10. therefore a technique as shown in figure 11 is required to eliminate the dead zone of load line at light load condition. + - 0.8v v ref sum/n + - vid125 rt9401 vid [0 : 4] v core r adj pi fb comp i x dac_out ) sum(i 3 1 x current mirror 1/2 i ofs i ofs r vid125 r fb ovp 500mv
rt8800a 14 ds8800a-06 april 2011 www.richtek.com figure 13. gm4 setting for current ratio function. figure 14. gm1 to gm3 setting for current ratio function. rewriting equation (3), we get csn lx lx_valley comm f r r i r v the technique mentioned above also provides output voltage offset function specified by intel ? vrd10.x. the offset voltage level is calculated as: f csn adj offset v r r v = enough bias current is required for a schottky to act like a voltage source. users should choose the appropriate r cs based on the iv characteristic of the diode (figure 12) according to figure 12, the forward voltage of diode will be different results from the different conduction current. so when the characteristic of diode in the circuit you design is in zone 1, this will result in spec. mis-met. it is because when the v core is changed during dvid, the node v core - v f is also changed to produce the differential conduction current of diode i and the i will result in producing the differential forward voltage of diode v f referring to equation (1). the v f would get i x . then the v core must be subtracted the extra voltage v (ext) ( i x x r adj ) during dvid. so you will get the v core = v (max) - v (min) - v (ext) during dvid tests. in order to reduce the effect results from diode. the better choice is to decrease the rcs to increase the conduction current of diode i to get better v characteristic of diode in zone 2. over voltage protection (ovp) the rt8800a continuously monitors voltage at fb pin. ovp is triggered if fb voltage is 500mv higher than the voltage at pi pin. rt8800a latches off and turns on lower mosfet to protect the load from damage upon on ovp trip. it can only be reset by dvd and vdd pins. current ratio setting current ratio adjustment is possible as described below. it is important for achieving thermal balance in practical application where thermal conditions between phases are not identical. figure 13 shows the application circuit of gm for current ratio requirement. according to basic circuit theory, if lx lx px sx px x x px sx lx x r i r r r v then c ) //r (r r l + = = with other phase kept unchanged, this phase would share (r px +r sx )/r px times current than other phases. figure 14 and 15 show different current ratio setting for the power stage whe n phase 3 i s programmed 2 times current than other phases. figure 16 and 17 compare the above current ratio setting results. (4) figure 12 i v zone 1 zone 2 iv characteristic figure 13 t t l x r lx i lx + v out r sx c x + v x - r px i l3 1.5uh 1m 3k 1uf 3k 1.5uh 1m 1.5k 1uf i l1 to l2
rt8800a 15 ds8800a-06 april 2011 www.richtek.com design procedure suggestion a.output filter pole and zero (inductor, output capacitor value & esr). b.error amplifier compensation & sawtooth wave amp- litude (compensation network). current loop setting a.gm amplifier s/h current (current sense component dcr, icommon pin external resistor value). b.over-current protection trip point (r icommon1 resistor). vrm load line setting a.droop amplitude (pi pin resistor). b.no load offset (r icommon2 ) figure 15 figure 16 power sequence & ss dvd pin external resistor and ss pin capacitor. pcb layout a.sense for current sense gm amplifier input. b.refer to layout guide for other items. voltage loop setting design example given: apply for four phase converter v in = 12v v core = 1.5v i load(max) = 100a v droop = 100mv at full load (1m load line) ocp trip point set at 35a for each channel (s/h) dcr = 1m of inductor at 25 c l = 1.5 h c out = 8000 f with 5m equivalent esr. 1. compensation setting a. modulator gain, pole and zero: from the following formula: modulator gain =v in /v ramp =12/2.4=5 (i.e 14db) where v ramp : ramp amplitude of saw-tooth wave lc filter pole = 1.45khz and esr zero =3.98khz b. ea compensation network: select r1 = 4.7k, r2 = 15k, c1 = 12nf, c2 = 68pf and use the type 2 compensation scheme shown in figure 21. by calculation, the f z = 0.88khz, f p = 322khz and middle band gain is 3.19 (i.e 10.07db). current ratio function 0 5 10 15 20 25 30 35 40 45 0 153045607590 i core (a) i lx (a) i l1 i l2 i l3 current balance function 0 5 10 15 20 25 30 35 40 0 20406080100 i core (a) i lx (a) i l1 i l2 i l3 figure 17. type 2 compensation network of ea ea rb2 rb1 + - 15k c1 12nf c2 68pf 4.7k
rt8800a 16 ds8800a-06 april 2011 www.richtek.com layout considerations place the high-power switching components first, and separate them from sensitive nodes. 1. most critical path: the current sense circuit is the most sensitive part of the converter. the current sense resistors tied to isp1,2,3 and icommon should be located not more than 0.5 inch from the ic and away from the noise switching nodes. the pcb trace of sense nodes should figure 18. power stage ripple current path sw2 l2 sw1 l1 c out r l v out v in r in c in v 2. over-current protection setting consider the temperature coefficient of copper 3900ppm/ c, 35.6a i a 150 330 1.39m i a 150 r dcr i l l icommon1 l = = = be parallel and as short as possible. r&c filter of choke should place close to pwm and the r & c connect directly to the pin of each output choke, use 10 mil differencial pair, and 20 mil gap to other phase pair. less via as possible. 2. switching ripple current path: a. input capacitor to high side mosfet. b. low side mosfet to output capacitor. c. the return path of input and output capacitor. d. separate the power and signal gnd. e. the switching nodes (the connection node of high/ low side mosfet and inductor) is the most noisy points. keep them away from sensitive small-signal node. f . reduce parasitic r, l by minimum length, enough copper thickness and avoiding of via. 3. mosfet driver should be closed to mosfet.
rt8800a 17 ds8800a-06 april 2011 www.richtek.com figure 19. layout consideration figure 20 pwm rt pi vcc comp fb rt8800a cspx +5v in c bp c c r icom c out r c r fb next to ic locate next to fb pin l o1 v core c in locate near mosfets c boot +12v or +5v 0.1uf +12v vcc vin gnd bst drvh sw drvl rt9603 next to ic gnd gnd icommon r drd
rt8800a 18 ds8800a-06 april 2011 www.richtek.com figure 21 figure 22
rt8800a 19 ds8800a-06 april 2011 www.richtek.com figure 23
rt8800a 20 ds8800a-06 april 2011 www.richtek.com information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com outline dimension a a1 a3 d e 1 d2 e2 l b e see detail a dimensions in millimeters dimensions in inches symbol min max min max a 0.800 1.000 0.031 0.039 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 d 2.950 3.050 0.116 0.120 d2 1.300 1.750 0.051 0.069 e 2.950 3.050 0.116 0.120 e2 1.300 1.750 0.051 0.069 e 0.500 0.020 l 0.350 0.450 0.014 0.018 v-type 16l qfn 3x3 package note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options 1 1 2 2

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